Static random access memories (SRAMs) may be designed as asynchronous or synchronous devices. The timing of an asynchronous SRAM typically operates in response to externally provided signals. For example, it is known in the prior art for asynchronous SRAMs to generate an internal timing signal in response to a change in address. Commonly-owned U.S. Pat. No. 5,306,958, entitled HIGH-SPEED ADDRESS TRANSITION DETECTION CIRCUIT and filed on May 6, 1992, discloses an address transition detection circuit for generating a timing pulse in response to either a low-to-high or high-to-low external address input transition.
Unlike asynchronous SRAMs, most signals in synchronous SRAMs are referenced to an external system clock. Input and output signals are latched synchronous with the system clock. While asynchronous SRAMs are presently more common than synchronous SRAMs, increasingly, more computer systems are designed to employ synchronous SRAMs (typically as cache memory for a microprocessor).
A consequence of the two different types SRAMs (synchronous and asynchronous) is that integrated circuit and systems manufacturers must employ different test programs and/or machines for the two different types of SRAMs.
U.S. Pat. No. 5,124,589 issued to Shiomi et al. on Jun. 23, 1992 discloses an SRAM device capable of synchronous and asynchronous operations. Shiomi et al. illustrates both bipolar and BiCMOS embodiments of an asynchronous SRAM having additional input and output circuits. A signal (TH) of a predetermined level is used to disable a latch function of input and output circuits allowing externally supplied signals to the circuits to pass through. The input and output circuits include master and slave registers. The Shiomi et al. device has separate data inputs and outputs. During synchronous operation of the Shiomi et al. device the master register latches on the rising edge of a clock signal while the slave register is disabled. On the subsequent falling edge of the clock signal the slave register is latched and the master register is disabled.
In a bipolar embodiment of the Shiomi et al. patent, the disabling circuit requires a signal TH greater than the VEE voltage for the circuit. In a BiCMOS embodiment the disabling circuit requires a third voltage for placing an NMOS device into non-saturation. In both the bipolar and BiCMOS illustrations the third voltage is either provided separately via an additional pad or separate circuit provided to generate the voltage on the chip.